The present invention relates to flash memory devices and, more particularly, to a flash memory device that combines executable and non-executable memory on a common semiconductor die.
Flash memory is a well-known data storage technology that is widely used for non-volatile data storage. Generally speaking, there are two classes of flash memory devices: random access devices and serial access devices.
Random-access flash devices are devices that can be randomly accessed for reading. Any storage bit within such a device can be directly accessed for reading by providing the address of the bit on the device pins and then immediately getting the requested bit value (without the device having to first internally access non-requested cells or to go through a sequence of command codes). There are two main types of random-access flash devices. One type of random-access flash device uses flash cells with conductive floating gates. Examples of this type of flash device include NOR devices, such as those manufactured and sold by Intel, AMD and other companies. The other type of random-access flash device uses flash cells with insulating floating gates. Examples of this type of flash device include the MirrorBit devices manufactured and sold by AMD (also offered by Fujitsu under the name MirrorFlash) and the NROM devices manufactured and sold by Saifun Semiconductors of Netanya, Israel.
Serial-access flash devices are devices in which the above is not valid. Storage bits within such a device can not be directly accessed for reading. When the value of a bit has to be read, the device receives an address identifying a relatively large chunk of bits (typically a sector of 512 bytes=4096 bits), all the bits in the chunk are accessed and loaded into an internal RAM buffer within the device, and only then it is possible to get the value of the requested bit by providing its location within the chunk of data in the buffer. Example of such serial-access flash devices include NAND devices, such as those manufactured and sold by Toshiba, Samsung and other companies.
One advantage of serial access flash devices over random access flash devices is that serial access devices are more compact than comparable random access devices. This is because, with no need to access each bit individually, both the cells and the associated decoding and driving circuitry of a serial access device are smaller than the cells and the decoding and driving circuitry of a comparable random access device. A serial access device thus packs more bits into the same semiconductor area than a comparable random access device and costs less per bit than a comparable random access device.
N. B.: The above description treats the flash devices as storing independent bits. Most flash devices are actually organized in 8-bit bytes or 16-bits words (i.e. even in a random-access device it is not possible to read just a single bit and the minimum group of bits that can be accessed is a byte or a word). However, this detail has no significance for the present invention and therefore the single bit picture has been used above for illustrational simplicity.
N. B.: Flash cells can be either binary (i.e. one bit per cell) or multi-level (i.e. more than one bit per cell) as in Harari, U.S. Pat. No. 5,043,940 and in Assar et al., U.S. Pat. No. 5,596,526. The present invention is applicable to both kinds of flash cells, even though for illustrational simplicity the explanations above are in terms of binary cells.
Another way to classify flash memory devices is according to whether or not they are executable. An “executable” flash device is a flash device in which computer machine code can be stored and directly executed in place without first being copied to some other memory device. The two classifications, random-access vs. serial-access and executable vs. non-executable, are not independent, as can be seen from the following three considerations:                1. Both random-access flash memory devices and serial-access flash memory devices can be used for data storage.        2. Computer code is just a particular type of data, that can be stored either in a random-access flash memory device or in a serial-access flash memory device.        3. Only random-access memory devices are executable. This is because while executing the code, the executing processor needs to access random locations within the memory. For example, a JUMP command in the code makes the processor ask for a next location that can be far away from the previous location.        
Modern cellular telephones, personal data assistants (PDAs) and similar electronic devices need to store both code and non-code data. There are at least four ways to do this using flash memory devices:                1. Use a first flash memory device, which may be executable or non-executable, for non-code data storage. Use a second, executable flash memory device for code storage. Execute the code in-place from the second device.        2. Use a first flash memory device, which may be executable or non-executable, for non-code data storage. Use a second flash memory device, which also may be executable or non-executable, for code storage. The code to be executed is copied from the second flash memory device to a volatile random access memory (RAM) and is executed from the RAM. This design requires at least a small amount of executable non-volatile memory for executing the system's boot code on start-up. This boot code memory can be either in the second flash memory device (if the second flash memory device is executable) or in a separate integrated circuit.        3. Use a single, executable flash memory device to store both code and non-code data. The code is executed in-place from the flash memory device.        4. Use only one flash memory device, which may be executable or non-executable, to store both code and non-code data. The code to be executed is copied from the flash memory device to RAM and is executed from the RAM. As in the second option, there must be at least a small amount of executable non-volatile memory for executing boot code.        
Each of these four architectures has its own respective advantages and disadvantages. All four architectures are in use today. However, as reducing manufacturing costs becomes more and more important, there is a clear advantage to the third architecture above that uses a single flash integrated circuit rather than two integrated circuits and that does not require adding extra RAM from which to execute the code. Therefore, recently, more and more cellular phones and PDAs are being made with only one flash memory device, from which flash memory device the code is executed directly in-place.
Nevertheless, there is an inherent problem in the configuration that executes code on the same flash memory device in which non-code data are stored. When non-code data are written or erased, the flash memory device requires a relatively long time to complete the write or erase operation. For example, in a typical NOR flash device, reading takes tens of nanoseconds per randomly read data unit (byte or word, depending on the specific device architecture), writing takes a few microseconds per randomly written data unit (byte or word) and erasing, which is done in units of entire blocks (typically 64 Kilobytes per block), takes hundreds of milliseconds. While a flash memory device is occupied with writing or erasing, it may not be able to respond to read requests for code to be executed. The execution of code that invokes a write or erase operation could actually block the continued execution of other code, resulting in a cellular telephone or PDA with this kind of memory configuration hanging.
Two methods are employed in the prior art to overcome this problem.
The first method is to split the executable flash memory device into two or more separate portions, often referred to as “partitions”, that are capable of independent operation. In this context, “independence” means that even though a write/erase operation is taking place in one partition, a read request from another paltition can still be served immediately without waiting for write/erase completion and without interfering with the write/erase operation. This capability is called “Read While Write” or “RWW” by some flash vendors. A flash memory device that supports such capability stores and executes the code in one partition and stores the non-code data in another partition. Both Intel and AMD offer such devices. It should be noted that each partition is capable of supporting either code or non-code data, and it is up to the system designer to decide where to keep the code and where to keep the non-code data (of course making sure the processor is directed to a code section upon system boot).
The second method is to use software to “shield” the flash memory device from the problem by guaranteeing that in-place code execution never overlaps flash write or flash erase in time. Such solutions are not trivial and require some clever programming. Simply put, the flash supporting software copies some of its flash access code into RAM, and then when a write/erase operation is initiated, the flash supporting software makes sure the only code that runs during the operation time is code executed from RAM. Because the system might receive high priority external interrupts that require immediate handling and cannot wait for the completion of the flash operation (e.g. getting an incoming call in a cellular telephone), the flash supporting software must disable interrupts before starting the write/erase operation (to keep the processor from jumping to the interrupt service routine) and must continuously monitor for incoming interrupts. If such an interrupt is detected, the flash Support software suspends the write/erase operation, allows the interrupt to be serviced, and then resumes the operation. Compared to the first method, this method is not easy to configure and port to new flash memory devices; but this is the only option for a flash memory device that lacks RWW capability. Intel offers two software packages, called FDI and PSM, for supporting its flash memory devices, that work according to these principles.
There remains a major deficiency in the flash devices used in systems that have the third architecture described above (one flash memory device for both code and non-code data, with code executed in place). Even though only a portion of the flash memory device is used for code execution and so needs to be executable, all portions of the flash memory device are fully executable. This is a disadvantage because executable flash memory occupies more area on a semiconductor die than equivalent non-executable flash memory. This extra cost of “executability” is paid even for portions of the flash memory that do not require it. Some semiconductor manufacturers (e.g., Samsung) recognize this deficiency and offer flash packages that are assemblies of multiple flash dies, some of which are executable and some of which are not executable. However, such “Multi-Chip Packages” offer a less than satisfactory solution to this problem, for several reasons. These packages usually are larger in height than conventional integrated circuits; their assembly costs are higher than the assembly costs of conventional integrated circuits; and they are generally less convenient to work with than conventional flash memory integrated circuits because they include flash dies of disparate technologies that require different interfacing and access methods.
There is thus a widely recognized need for, and it would be highly advantageous to have, a RWW flash memory device that would overcome the disadvantages of presently known RWW flash memory devices as described above.